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ds07-12519-2e fujitsu semiconductor data sheet 8-bit proprietary microcontroller cmos f 2 mc-8l mb89660 series mb89663/665/p665/w665 n description the mb89660 series has been developed as a general-purpose version of the f 2 mc*-8l family consisting of proprietary 8-bit single-chip microcontrollers. in addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions such as timers, a uart, a serial interface, an 8-bit a/d converter, an input capture, an output compare, and an external interrupt. the mb89660 series is applicable to a wide range of applications from welfare products to industrial equipment. *: f 2 mc stands for fujitsu flexible microcontroller. n features ? package expansion qfp package sdip package (continued) n pac k ag e 64-pin plastic sh-dip (dip-64p-m01) 64-pin plastic qfp (dip-64c-a06) 64-pin ceramic sh-dip (fpt-64p-m06)
mb89660 series 2 (continued) ?f 2 mc-8l family cpu core multiplication and division instructions 16-bit arithmetic operations test and branch instructions bit manipulation instructions, etc. ? three types of timers 8-bit pwm timer 8/16-bit timer/counter 20-bit time-base timer ? functions that permit communications with a variety of devices uart which permits selection of synchronous/asynchronous communications a serial interface that permits selection of the transfer direction ? 8-bit a/d converter: 8 channels sense mode function capable of performing compare operation in 5 m s activation by external input possible ? real-time control input capture: 2 channels output compare: 2 channels ? external interrupt: 4 channels two channels are independent and capable of wake-up from low-power consumption modes (with an edge detection function). ? low power consumption modes stop mode (oscillation stops to minimize the current consumption.) sleep mode (the cpu stops to reduce the current consumption to approx. 1/3 of normal.) hardware standby mode (wake-up from this mode and activation by pin input only.) instruction set optimized for controllers
mb89660 series 3 n product lineup (continued) mb89665 mb89w665 mb89p665 classification mass production products (mask rom products) eprom product one-time prom product, also used for evaluation rom size 8 k 8 bits (internal mask rom) 16 k 8 bits (internal mask rom) 16 k 8 bits (internal prom, programming with general-purpose eprom programmer) 16 k 8 bits (internal prom, programming with general-purpose eprom programmer) ram size 256 8 bits 512 8 bits cpu functions number of instructions: 136 instruction bit length: 8 bits instruction length: 1 to 3 bytes data bit length: 1,8, 16 bits minimum execution time: 0.4 m s/10 mhz interrupt processing time: 3.6 m s/10 mhz ports output ports (cmos): 8 output ports (n-ch open-drain): 8 (all also serve as peripherals.) i/o ports (cmos): 36 (19 ports also serve as peripherals.) to t a l : 5 2 8-bit pwm timer 8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 m s, 6.4 m s, 25.6 m s) 8-bit resolution pwm operation (conversion cycle: 102 m s, 1.6 ms, 6.6 ms) 8/16-bit timer/ counter independent 8-bit reload timer/counter operation: 2 channels single 16-bit event counter (cascade connection): 1 channel one clock selectable from four transfer clocks (one external shift clock, three internal clocks: 0.8 m s, 3.2 m s, 12.8 m s) uart 8 bits full-duplex double buffer synchronous and asynchronous data transfer 8-bit serial i/o 8 bits lsb first/msb first selectability one clock selectable from four transfer clocks (one external shift clock, three internal shift clocks: 0.8 m s, 3.2 m s, 12.8 m s) 8-bit a/d converter 8-bit resolution 8 channels a/d conversion mode (conversion time: 18 m s at 10 mhz) sense mode (conversion time: 5 m s at 10 mhz) continuous activation by an external activation or an internal timer capable reference voltage input real-time i/o 16-bit timer: operating clock cycle (0.4 m s, 0.8 m s, 1.6 m s, 3.2 m s) overflow interrupt input capture: 16 bits 2 channels (external trigger edge selectability) output compare: 16 bits 2 channels mb89663 parameter part number
mb89660 series 4 (continued) * : varies with conditions such as the operating frequency. (see section n electrical characteristics.) n package and corresponding products : available : not available note: for more information about each package, see section n package dimensions. mb89665 mb89w665 mb89p665 external interrupt 4 channels (edge selection, interrupt vector, source flag) rising edge/falling edge/both edges selectability used also for wake-up from stop/sleep mode. (edge detection is also permitted in stop mode.) (wake-up from hardware standby mode is not possible) standby mode sleep mode, stop mode, and hardware standby mode process cmos operating voltage* 2.2 v to 6.0 v 2.7 v to 6.0 v package mb89663 mb89665 mb89p665 mb89w665 dip-64p-m01 dip-64c-a06 fpt-64p-m06 mb89663 parameter part number
mb89660 series 5 n differences among products 1. memory size before evaluating using the otprom (one-time prom) product (also used for evaluation), verify its differences from the product that will actually be used: take particular care on the following points: ? on the mb89663, register bank from 16 to 32 cannot be used. ? on the mb89p665, address bff0 h to bff6 h comprise the option setting area, option settings can be read by reading these addresses. ? the stack area, etc., is used. 2. current consumption ? when operated at low speed, the product with an otprom or an eprom will consume more current than the product with a mask rom. ? however, the current comsumption in sleep/stop modes is the same. (for more information, see sections n electrical characteristics and n example characteristics. 3. mask options functions that can be selected as options and how to designate these options vary by the product. before using options check section n mask options. take particular care on the following points: ? on the mb89p665, a pull-up resistor must be selected in a group of four pins for p54 to p57. ? for all products, p50 to p57 must be set to without a pull-up resistor when an a/d converter is used.
mb89660 series 6 n pin assignment (dip-64p-m01) (dip-64c-a06) (top view) 1 p36/rto1 2 p37/adst 3 p40/sck1 4 p41/so1 5 p42/si1 6 p43/sck2 7 p44/so2 8 p45/si2 9 p46/pto 10 p47 11 p50/an0 12 p51/an1 13 p52/an2 14 p53/an3 15 p54/an4 16 p55/an5 17 p56/an6 18 p57/an7 19 av cc 20 avr 21 av ss 22 p60/int0 23 p61/int1 24 p62/int2 25 p63/int3 26 hst 27 rst 28 mod0 29 mod1 30 x0 31 x1 32 v ss v cc 64 p35/rto0 63 p34/rti1 62 p33/rti0 61 p32/to2 60 p31/to1 59 p30/ec 58 v ss 57 p00 56 p01 55 p02 54 p03 53 p04 52 p05 51 p06 50 p07 49 p10 48 p11 47 p12 46 p13 45 p14 44 p15 43 p16 42 p17 41 p20 40 p21 39 p22 38 p23 37 p24 36 p25 35 p26 34 p27 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 p45/si2 p46/pto p47 p50/an0 p51/an1 p52/an2 p53/an3 p54/an4 p55/an5 p56/an6 p57/an7 av cc avr av ss p60/int0 p61/int1 p62/int2 p63/int3 hst 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p30/ec v ss p00 p01 p02 p03 p04 p05 p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 p20 64 63 62 61 60 59 58 57 56 55 54 53 52 p44/so2 p43/sck2 p42/si1 p41/so1 p40/sck1 p37/adst p36/rto1 v cc p35/rto0 p34/rti1 p33/rti0 p32/to2 p31/to1 20 21 22 23 24 25 26 27 28 29 30 31 32 rst mod0 mod1 x0 x1 v ss p27 p26 p25 p24 p23 p22 p21 (fpt-64p-m06) (top view)
mb89660 series 7 n pin description (continued) *1: dip-64p-m01, dip-64c-a06 *2: fpt-64p-m06 pin no. pin name circuit type function dip *1 qfp *2 30 23 x0 a crystal oscillator pins 31 24 x1 28 21 mod0 b operating mode selection pins connect directly to v cc or v ss . a pull-down resistor is selectable as an option for mask rom products. 29 22 mod1 27 20 rst c reset i/o pin this port is an n-ch open-drain output type with pull-up resistor and a hysteresis input type. l is output from this pin by an internal reset source. the internal circuit is initialized by the input of l. 26 19 hst g hardware standby input pin connect directly to v cc when hardware standby is not used. 56 to 49 49 to 42 p00 to p07 d general-purpose i/o ports 48 to 41 41 to 34 p10 to p17 40 to 33 33 to 26 p20 to p27 f general-purpose output ports 58 51 p30/ec e general-purpose i/o port also serves as an external clock input for an 8/16-bit timer/counter. this pin is a hysteresis input type and with a noise canceller. 59 52 p31/to1 e general-purpose high-current i/o port also serves as an 8/16-bit timer/counter output. this pin is a hysteresis input type and with a noise canceller. 60 53 p32/to2 e general-purpose i/o port also serves as an 8/16-bit timer/counter output. this pin is a hysteresis input type and with a noise canceller. 61 54 p33/rti0 e general-purpose i/o ports also serve as the data input for the input capture. this pin is a hysteresis input type and with a noise canceller. 62 55 p34/rti1 63 56 p35/rto0 e general-purpose i/o ports also serve as the data output for the output compare. this pin is a hysteresis input type and with a noise canceller. 158p36/rto1 2 59 p37/adst e general-purpose heavy-current i/o port also serves as the external activation input for the a/d converter. this pin is a hysteresis input type and with a noise canceller.
mb89660 series 8 (continued) *1: dip-64p-m01, dip-64c-a06 *2: fpt-64p-m06 pin no. pin name circuit type function dip *1 qfp *2 3 60 p40/sck1 e general-purpose i/o port also serves as the clock i/o for the uart. this pin is a hysteresis input type and with a noise canceller. 4 61 p41/so1 e general-purpose i/o port also serves as the data output for the uart. this pin is a hysteresis input type and with a noise canceller. 5 62 p42/si1 e general-purpose i/o port also serves as the data input for the uart. this pin is a hysteresis input type and with a noise canceller. 6 63 p43/sck2 e general-purpose i/o port also serves as the clock i/o for the 8-bit serial i/o interface. this pin is a hysteresis input type and with a noise canceller. 7 64 p44/so2 e general-purpose i/o port also serves as the data output for the 8-bit serial i/o interface. this pin is a hysteresis input type and with a noise canceller. 8 1 p45/si2 e general-purpose i/o port also serves as the data input for the 8-bit serial i/o interface. this pin is a hysteresis input type and with a noise canceller. 9 2 p46/pto e general-purpose i/o port also serves as a toggle output for an 8-bit pwm timer. this pin is a hysteresis input type and with a noise canceller. 10 3 p47 e general-purpose i/o port this pin is a hysteresis input type and with a noise canceller. 11 to 18 4 to 11 p50/an0 to p57/an7 h n-ch open-drain output-only ports also serve as the analog input for the a/d converter. 22 to 25 15 to 18 p60/int0 to p63/int3 e general-purpose i/o ports these pins also serve as an external interrupt input. these pins are a hysteresis input type and with a noise canceller. 64 57 v cc power supply pin 32 57 25 50 v ss power supply (gnd) pins 19 12 av cc a/d converter power supply pin 20 13 avr a/d converter reference voltage input pin 21 14 av ss a/d converter power supply pin use this pin at the same voltage as v ss .
mb89660 series 9 n i/o circuit type (continued) type circuit remarks a ? external clock input selection versions of crystal or ceramic oscillation type ? at an oscillation feedback resistor of approximately 1 m w /5.0 v b ? cmos input ? built-in pull-down resistor (mask rom products only) c ? at an output pull-up resistor (p-ch) of approximately 50 k w /5.0 v ? hysteresis input d ? cmos output ? cmos input ? pull-up resistor optional e ? cmos output ? hysteresis input ? pull-up resistor optional f ? cmos output x1 x0 standby control signal r p-ch n-ch p-ch n-ch p-ch r p-ch n-ch p-ch r p-ch n-ch
mb89660 series 10 (continued) type circuit remarks g ? hysteresis input h ? n-ch open-drain output ? analog input ? pull-up resistor optional p-ch n-ch p-ch r analog input
mb89660 series 11 n handling devices 1. preventing latchup latchup may occur on cmos ics if voltage higher than v cc or lower than v ss is applied to input and output pins other than medium- or high-voltage pins or if higher than the voltage which shows on 1. absolute maximum ratings in section n electrical characteristics is applied between v cc and v ss . when latchup occurs, power supply current increases rapidly and might thermally damage elements. when using, take great care not to exceed the absolute maximum ratings. also take care to prevent the analog power supply (av cc and avr) and analog input from exceeding the digital power supply (v cc ) when the analog system power supply is turned on and off. 2. treatment of unused input pins leaving unused input pins open could cause malfunctions. they should be connected to a pull-up or pull-down resistor. 3. treatment of power supply pins on microcontrollers with a/d converters connect to be av cc = v cc and av ss = avr = v ss if the a/d converters are not in use. 4. power supply voltage fluctuations although v cc power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. stabilizing voltage supplied to the ic is therefore important. as stabilization guidelines, it is recommended to control power so that v cc ripple fluctuations (p-p value) will be less than 10% of the standard v cc value at the commercial frequency(50 to 60 hz) and the transient fluctuation rate will be less than 0.1 v/ms at the time of a momentary fluctuation such as when power is switched. 5. precautions when using an external clock even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and wake-up from stop mode.
mb89660 series 12 n programming to the eprom on the mb89p665 the mb89p665 is an otprom version of the mb89660 series. 1. features ? 16-kbyte prom on chip ? options can be set using the eprom programmer. ? equivalency to the mbm27c256a in eprom mode (when programmed with the eprom programmer) 2. memory space memory space in each mode such as 16-kbyte prom, option area is diagrammed below. 0000 h 0080 h 0280 h bff0 h bff7 h c000 h ffff h single chip i/o ram not available not available not availble prom 16 kb 0000 h 3ff0 h 3ff7 h 4000 h 7fff h eprom mode (corresponding addresses on the eprom programmer) option area eprom 16 kb vacancy (read value ff h ) vacancy (read value ff h ) address
mb89660 series 13 3. programming to the prom in eprom mode, the mb89p665a functions equivalent to the mbm27c256a. this allows the prom to be programmed with a general-purpose eprom programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. programming procedure (1) set the eprom programmer to the mbm27c256a. (2) load program data into the eprom programmer at 4000 h to 7fff h (note that addresses c000 h to ffff h while operating as a single chip assign to 4000 h to 7fff h in eprom mode). load option data into addresses 3ff0 h to 3ff6 h of the eprom programmer. (for information about each corresponding option, see 8. setting otprom options.) (3) program with the eprom programmer. 4. recommended screening conditions high-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked otprom microcomputer program. program, verify aging +150?, 48 hrs. data verification assembly
mb89660 series 14 5. programming yield all bits cannot be programmed at fujitsu shipping test to a blanked otprom microcomputer, due to its nature. for this reason, a programming yield of 100% cannot be assured at all times. 6. erasure procedure in order to clear all locations of their programmed contents, it is necessary to expose the internal eprom to an ultraviolet light source. a dosage of 10 w-seconds/cm 2 is required to completely erase an internal eprom. this dosage can be obtained by exposure to an ultraviolet lamp (wavelength of 2537 angstroms (?)) with intensity of 12000 m w/cm 2 for 15 to 21 minuites. the internal eprom should be about one inch from the source and all filters should be removed from the uv light source prior to erasure. it is important to note that the internal eprom and similar devices, will erase with light sources having wave- lengths shorter than 4000 ?. although erasure time will be much longer than with uv source at 2537 ?, nevertheless the exposure to fluorescent light and sunlight will eventually erase the internal eprom, and exposure to them should be prevented to realize maximum system reliability. if used in such an environment, the package windows should be covered by an opaque label or substance. 7. eprom programmer socket adapter inquiry: sun hayato co., ltd.: tel 81-3-3802-5760 note: connect the adapter jumper pin to v ss when using. package compatible socket adapter fpt-64p-m06 rom-64qf-28dp-8l dip-64p-m01 rom-64sd-28dp-8l
mb89660 series 15 8. setting otprom options the programming procedure is the same as that for the prom. options can be set by programming values at the addresses shown on the memory map. the relationship between bits and options is shown on the following bit map: ? otprom option bit map note: ? set each bit to erase. ? do not write 0 to the vacant bit. the read value of the vacant bit is 1, unless 0 is written to it. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 3ff0 h vacancy readable and writable vacancy readable and writable vacancy readable and writable oscillation stabilization time 1: crystal 0: ceramic reset pin output 1: yes 0: no power-on reset 1: yes 0: no vacancy readable and writable vacancy readable and writable 3ff1 h p07 pull-up 1: no 1: yes p06 pull-up 1: no 1: yes p05 pull-up 1: no 0: yes p04 pull-up 1: no 0: yes p03 pull-up 1: no 0: yes p02 pull-up 1: no 0: yes p01 pull-up 1: no 0: yes p00 pull-up 1: no 0: yes 3ff2 h p17 pull-up 1: no 0: yes p16 pull-up 1: no 0: yes p15 pull-up 1: no 0: yes p14 pull-up 1: no 0: yes p13 pull-up 1: no 0: yes p12 pull-up 1: no 0: yes p11 pull-up 1: no 0: yes p10 pull-up 1: no 0: yes 3ff3 h p37 pull-up 1: no 0: yes p36 pull-up 1: no 0: yes p35 pull-up 1: no 0: yes p34 pull-up 1: no 0: yes p33 pull-up 1: no 0: yes p32 pull-up 1: no 0: yes p31 pull-up 1: no 0: yes p30 pull-up 1: no 0: yes 3ff4 h p47 pull-up 1: no 0: yes p46 pull-up 1: no 0: yes p45 pull-up 1: no 0: yes p44 pull-up 1: no 0: yes p43 pull-up 1: no 0: yes p42 pull-up 1: no 0: yes p41 pull-up 1: no 0: yes p40 pull-up 1: no 0: yes 3ff5 h vacancy readable and writable vacancy readable and writable vacancy readable and writable p57 to p54 pull-up 1: no 0: yes p53 pull-up 1: no 0: yes p52 pull-up 1: no 0: yes p51 pull-up 1: no 0: yes p50 pull-up 1: no 0: yes 3ff6 h vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable p63 pull-up 1: no 0: yes p62 pull-up 1: no 0: yes p61 pull-up 1: no 0: yes p60 pull-up 1: no 0: yes
mb89660 series 16 n block diagram x0 x1 oscillator rst clock controller reset circuit (wdt) 8 8 p00 to p07 p10 to p17 cmos i/o port cmos output port ram f 2 mc-8l cpu rom 21-bit time-base timer 8-bit pwm timer uart port 4 cmos i/o port n-ch open-drain output port 8-bit a/d converter 4 4 external interrupt cmos i/o port p60/int0 to p63/int3 8 avr av cc av ss 8 p50/an0 to p57/an7 p44/so2 p45/si2 p46/pto internal bus hst hardware standby v cc , v ss 2 mod0, mod1 other pins p47 8-bit serial i/o p43/sck2 p41/so1 p42/si1 p40/sck1 p35/rto0 p36/rto1 output compare cmos i/o port 16-bit timer input capture p33/rti0 p34/rti1 p31/to1 p32/to2 p30/ec 8/16-bit timer/counter real-time i/o p37/adst port 0 and port 1 port 3 port 2 port 5 port 6 8 p20 to p27
mb89660 series 17 n cpu core 1. memory space the microcontrollers of the mb89660 series offer a memory space of 64 kbytes for storing all of i/o, data, and program areas. the i/o area is located at the lowest address. the data area is provided immediately above the i/o area. the data area can be divided into register, stack, and direct areas according to the application. the program area is located at exactly the opposite end, that is, near the highest address. provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. the memory space of the mb89660 series is structured as illustrated below. memory space 0000 h 0080 h 0100 h 0180 h e000 h ffff h mb89663 i/o ram 256 b register 0000 h 0080 h 0100 h 0200 h c000 h ffff h mb89665 mb89w665 mb89p665 i/o ram 512 b register rom* 16 kb not available not available 0280 h *: when the mb89p665 is used for evaluation, the internal rom cannot be used. rom 8 kb
mb89660 series 18 2. registers the f 2 mc-8l family has two types of registers; dedicated registers in the cpu and general-purpose registers in the memory. the following dedicated registers are provided: program counter (pc): a 16-bit register for indicating instruction storage positions accumulator (a): a 16-bit temporary register for storing arithmetic operations, etc. when the instruction is an 8-bit data processing instruction, the lower byte is used. temporary accumulator (t): a 16-bit register which performs arithmetic operations with the accumulator when the instruction is an 8-bit data processing instruction, the lower byte is used. index register (ix): a 16-bit register for index modification extra pointer (ep): a 16-bit pointer for indicating a memory address stack pointer (sp): a 16-bit register for indicating a stack area program status (ps): a 16-bit register for storing a register pointer, a condition code the ps can further be divided into higher 8 bits for use as a register bank pointer (rp) and the lower 8 bits for use as a condition code register (ccr). (see the diagram below.) pc a t ix ep sp ps 16 bits : program counter : accumulator : temporary accumulator : index register : extra pointer : stack pointer : program status fffd h undefined undefined undefined undefined undefined i-flag = 0, il1, 0 = 11 other bits are undefined. initial value structure of the program status register vacancy h i il1, 0 n z vc 54 rp ps 109876 3210 15 14 13 12 11 rp ccr vacancy vacancy
mb89660 series 19 the rp indicates the address of the register bank currently in use. the relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. the ccr consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of cpu operations at the time of an interrupt. h-flag: set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. cleared otherwise. this flag is for decimal adjustment instructions. i-flag: interrupt is allowed when this flag is set to 1. interrupt is prohibited when the flag is set to 0. set to 0 when reset. il1, 0: indicates the level of the interrupt currently allowed. processes an interrupt only if its request level is higher than the value indicated by this bit. n-flag: set if the msb is set to 1 as the result of an arithmetic operation. cleared when the bit is set to 0. z-flag: set when an arithmetic operation results in 0. cleared otherwise. v-flag: set if the complement on 2 overflows as a result of an arithmetic operation. reset if the overflow does not occur. c-flag: set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. cleared otherwise. set to the shift-out value in the case of a shift instruction. il1 il0 interrupt level high-low 00 1 high low = no interrupt 01 10 2 11 3 rule for conversion of actual addresses of the general-purpose register area ? a15 ? a14 ? a13 ? a12 ? a11 ? a10 ? a9 ? a8 r4 a7 r3 a6 r2 a5 r1 a4 r0 a3 b2 a2 b1 a1 b0 a0 lower op codes rp generated addresses
mb89660 series 20 the following general-purpose registers are provided: general-purpose registers: an 8-bit register for storing data the general-purpose registers are 8 bits and located in the register banks of the memory. one bank contains eight registers. up to a total of 16 banks can be used on the mb89663 and a total of 32 banks can be used on the mb89665/p665/w665. the bank currently in use is indicated by the register bank pointer (rp). note: the number of register banks that can be used varies with the ram size. r1 r2 r3 r4 r5 r6 r7 this address = 0100 h + 8 (rp) memory area 32 banks r0 register bank configuration
mb89660 series 21 n i/o map (continued) address read/write register name register description 00 h (r/w) pdr0 port 0 data register 01 h (w) ddr0 port 0 data direction register 02 h (r/w) pdr1 port 1 data register 03 h (w) ddr1 port 1 data direction register 04 h (r/w) pdr2 port 2 data register 05 h vacancy 06 h vacancy 07 h vacancy 08 h (r/w) stbc standby control register 09 h (r/w) wdtc watchdog timer control register 0a h (r/w) tbtc watch interrupt control register 0b h vacancy 0c h (r/w) pdr3 port 3 data register 0d h (w) ddr3 port 3 data direction register 0e h (r/w) pdr4 port 4 data register 0f h (w) ddr4 port 4 data direction register 10 h (r/w) pdr5 port 5 data register 11 h vacancy 12 h (r/w) pdr6 port 6 data register 13 h (w) ddr6 port 6 data direction register 14 h vacancy 15 h (r/w) adc1 a/d converter control register 1 16 h (r/w) adc2 a/d converter control register 2 17 h (r/w) adcd a/d converter data register 18 h (r/w) t2cr 8/16-bit timer 2 control register 19 h (r/w) t1cr 8/16-bit timer 1 control register 1a h (r/w) t2dr 8/16-bit timer 2 data register 1b h (r/w) t1dr 8/16-bit timer 1 data register 1c h (r/w) cntr pwm control register 1d h (w) comr pwm compare register 1e h vacancy 1f h vacancy
mb89660 series 22 (continued) note: do not use vacancies. address read/write register name register description 20 h (r/w) smc uart serial mode control register 21 h (r/w) src uart serial rate control register 22 h (r/w) ssd uart serial status/data register 23 h (r/w) sidr/sodr uart serial data register 24 h (r/w) smr serial mode register 25 h (r/w) sdr serial data register 26 h (r/w) eic1 external interrupt control register 1 27 h (r/w) eic2 external interrupt control register 2 28 h (r/w) tmcr timer control register 29 h (r) tchr timer count register (h) 2a h (r) tclr timer count register (l) 2b h (r/w) opcr output control register 2c h (r/w) cpr0h output compare register 0 (h) 2d h (r/w) cpr0l output compare register 0 (l) 2e h (r/w) cpr1h output compare register 1 (h) 2f h (r/w) cpr1l output compare register 1 (l) 30 h (r/w) iccr input capture control register 31 h (r/w) icic input capture interrupt control register 32 h (r) icr0h input capture register 0 (h) 33 h (r) icr0l input capture register 0 (l) 34 h (r) icr1h input capture register 1 (h) 35 h (r) icr1l input capture register 1 (l) 36 h vacancy 37 h vacancy 38 h vacancy 7c h (w) ilr1 interrupt level setting register 1 7d h (w) ilr2 interrupt level setting register 2 7e h (w) ilr3 interrupt level setting register 3 7f h vacancy
mb89660 series 23 n electrical characteristics 1. absolute maximum ratings (av ss = v ss = 0.0 v) * : use av cc and v cc set at the same voltage. take care so that av cc does not exceed v cc , such as when power is turned on. precautions: permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol value unit remarks min. max. power supply voltage v cc av cc v ss C 0.3 v ss + 7.0 v * avr v ss C 0.3 v ss + 7.0 v avr must not exceed av cc + 0.3 v input voltage v i v ss C 0.3 v cc + 0.3 v output voltage v o v ss C 0.3 v cc + 0.3 v l level maximum output current i ol 20ma l level average output current i olav 4ma average value (operating current operating rate) l level total maximum output current s i ol 100ma l level total average output current s i olav 40ma average value (operating current operating rate) h level maximum output current i oh C20ma h level average output current i ohav C4ma average value (operating current operating rate) h level total maximum output current s i oh C50ma h level total average output current s i ohav C20ma average value (operating current operating rate) power consumption p d 300mw operating temperature t a C40 +85 c storage temperature tstg C55 +150 c
mb89660 series 24 2. recommended operating conditions (av ss = v ss = 0.0 v) * : these values vary with the operating frequency and analog assurance range. see figure. 1 and 5. a/d converter electrical characteristics. figure 1 operating voltage vs. main clock operating frequency (mhz) parameter symbol value unit remarks min. max. power supply voltage v cc av cc 2.2* 6.0* v normal operation assurance range* mb89663/665 2.7* 6.0* v normal operation assurance range* mb89p665 1.5 6.0 v retains the ram state in stop mode avr 0.0 av cc v operating temperature t a C40 +85 c 1 2 3 4 5 6 110 operating voltage (v) 5 234 6789 analog accuracy assured in the av cc = v cc = 3.5 to 6.0 v range main clock operating frequency (mhz) note: the shaded area is assured only for the mb89663/665. operation assurance range
mb89660 series 25 3. dc characteristics (av cc = v cc = +5.0 v, av ss = v ss = 0.0 v, t a = C40 c to +85 c) (continued) parameter symbol pin condition value unit remarks min. typ. max. h level input voltage v ih p00 to p07, p10 to p17 0.7 v cc v cc + 0.3 v v ihs rst , hst p30 to p37, p40 to p47, p60 to p63 0.8 v cc v cc + 0.3 v l level input voltage *1 v il p00 to p07, p10 to p17 v ss C 0.3 0.3 v cc v v ils rst , hst p30 to p37, p40 to p47, p60 to p63 v ss C 0.3 0.2 v cc v open-drain output pin application voltage v d p50 to p57 v ss C 0.3 v cc + 0.3 v h level output voltage v oh1 p00 to p07, p10 to p17, p20 to p27, p30, p32 to p36, p40 to p47, p60 to p63 i oh = C2.0 ma 2.4 v v oh2 p31, p37 i oh = C15 ma 2.4 v l level output voltage v ol1 p00 to p07, p10 to p17, p20 to p27, p30, p32 to p36, p40 to p47, p50 to p57, p60 to p63 i ol = +1.8 ma 0.4v v ol2 p31, p37 i ol = +12 ma 0.4v v ol3 rst i ol = +4.0 ma 0.4v input leakage current (hi-z output leakage current) i li1 p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p60 to p63 0.45 v < v i < v cc 5 m a without pull-up resistor pull-up resistance r pulu rst , option selection pin v i = 0.0 v 25 50 100 k w
mb89660 series 26 (continued) (av cc = v cc = +5.0 v, av ss = v ss = 0.0 v, t a = C40 c to +85 c) *1: fix mod0 and mod1 to v ss . *2: the power supply current is measured at the external clock. *3: for information on t inst , see (4) instruction cycle in 4. ac characteristics. parameter symbol pin condition value unit remarks min. typ. max. pull-down resistance r puld mod0, mod1 v i = +5.0 ma 5 20 60 k w mask rom products only power supply current i cc v cc f c = 10 mhz t inst *3 = 0.4 m s normal mode 1518ma mb89663/665 1720ma mb89p665/ w665 i ccs f c = 10 mhz t inst *3 = 0.4 m s sleep mode 6 8ma i cch t a = +25 c t inst *3 = 0.4 m s stop mode 10 m a also applicable to the hardware standby mode. i a av cc f c = 10 mhz, when a/d conversion is activated 2.54.5ma i ah f c = 10 mhz, t a = +25 c, when a/d conversion is stopped 5 m a input capacitance c in other than av cc , av ss , v cc , and v ss f = 1 mhz 10 pf
mb89660 series 27 4. ac characteristics (1) reset timing, hardware standby timing (v cc = +5.0 v 10%, av ss =v ss = 0.0 v, t a = C40 c to +85 c) * : t xcyl is the oscillation cycle (1/f c ) to input to the x0 pin. (2) power-on reset (av ss = v ss = 0.0 v, t a = C40 c to +85 c) note: make sure that power supply rises within the selected oscillation stabilization time. if power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. parameter symbol condition value unit remarks min. max. rst l pulse width t zlzh 16 t xcyl ns hst l pulse width t hlhh 16 t xcyl ns parameter symbol condition values unit remarks min. max. power supply rising time t r 50ms power supply cut-off time t off 1ms due to repeated operations t zlzh 0.2 v cc 0.2 v cc rst t hlhh 0.2 v cc 0.2 v cc hst 0.2 v 0.2 v 2.0 v v cc 0.2 v t r t off
mb89660 series 28 (3) clock timing (av ss = v ss = 0.0 v, t a = C40 c to +85 c) (4) instruction cycle parameter symbol pin condition value unit remarks min. typ. max. clock frequency f c x0, x1 1 10 mhz clock cycle time t xcyl x0, x1 100 1000 ns input clock pulse width p wh p wl x0 20 ns external clock input clock rising/ falling time t cr t cf x0 10 ns external clock parameter symbol value (typical) unit remarks instruction cycle (minimum execution time) t inst 4/f c m s when operating at f c = 10 mhz 0.2 v cc 0.8 v cc x0 0.2 v cc t cr t cf 0.8 v cc 0.2 v cc x0 x1 x0 x1 when a crystal or ceramic resonator is used when an external clock is used open t xcyl p wh p wl x0 and x1 timing and conditions
mb89660 series 29 (5) recommended resonator manufacturers inquiry: fujitsu limited far part number (built-in capacitor type) frequency initial deviation of far frequency (t a = +25 c) temperature characteristic of far frequency (t a = C20 c to +60 c) far-c4cb-08000-m02 8.00 mhz 0.5% 0.5% far-c4cb-10000-m02 10.00 mhz 0.5% 0.5% sample application of piezoelectric resonator (far series) x0 x1 c1 c2 *: fujitsu acoustic resonator c1 = c2 = 20 pf? pf (built-in far) far*
mb89660 series 30 inquiry: kyocera corporation avx corporation north american sales headquarters: tel 1-803-448-9411 avx limited european sales headquarters: tel 44-1252-770000 avx/kyocera h.k. ltd. asian sales headquarters: tel 852-363-3303 murata mfg. co., ltd. murata electronics north america, inc.: tel 1-404-436-1300 murata europe management gmbh: tel 49-911-66870 murata electronics singapore (pte.) ltd.: tel 65-758-4233 resonator manufacturer* resonator frequency c1 (pf) c2 (pf) r (k w ) kyocera corporation kbr-7.68mws 7.68 mhz 33 33 kbr-8.0mws 8.0 mhz 33 33 murata mfg. co., ltd. csa8.00mtz 8.0 mhz 30 30 x0 x1 c1 c2 * sample application of ceramic resonator
mb89660 series 31 (6) serial i/o timing and uart timing (v cc = +5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst , see (4) instruction cycle. parameter symbol pin condition value unit remarks min. max. serial clock cycle time t scyc sck1, sck2 internal shift clock mode 2 t inst * m s sck1 ? so1 time sck2 ? so2 time t slov sck1, so1 sck2, so2 C200 200 ns valid si1 ? sck1 - valid si1 ? sck1 - t ivsh si1, sck1 si2, sck2 1/2 t inst * m s sck1 - ? valid si1 hold time sck2 - ? valid si2 hold time t shix sck1, si1 sck2, si2 1/2 t inst * m s serial clock h pulse width t shsl sck1, sck2 external shift clock mode 1 t inst * m s serial clock l pulse width t slsh sck1, sck2 1 t inst * m s sck1 ? so1 time sck2 ? so2 time t slov sck1, so1 sck2, so2 0 200 ns valid si1 ? sck1 - valid si2 ? sck2 - t ivsh si1, sck1 si2, sck2 1/2 t inst * m s sck1 - ? valid si1 hold time sck2 - ? valid si2 hold time t shix sck1, si1 sck2, si2 1/2 t inst * m s
mb89660 series 32 0.8 v 2.4 v t scyc t slov 0.2 v cc t shix 0.8 v t ivsh 0.8 v cc 0.2 v cc 0.8 v cc sck1 so1 si1 sck2 so2 si2 2.4 v 0.8 v t slsh 2.4 v t slov 0.2 v cc t shix 0.8 v cc 0.8 v t ivsh 0.8 v cc 0.2 v cc 0.8 v cc sck1 so1 si1 sck2 so2 si2 t shsl 0.8 v cc 0.2 v cc 0.2 v cc serial i/o timing and uart timing (internal shift clock mode) serial i/o timing and uart timing (external shift clock mode)
mb89660 series 33 (7) peripheral input timing (v cc = +5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst , see (4) instruction cycle. parameter symbol pin condition value unit remarks min. max. peripheral input h pulse width 1 t ilih1 rti0, 1 int0 to int3 2 t inst * m s peripheral input l pulse width 1 t ihil1 m s peripheral input h pulse width 2 t ilih2 ec 1 t inst * m s peripheral input l pulse width 2 t ihil2 m s peripheral input h pulse width 3 t ilih3 adst a/d mode 32 t inst * m s peripheral input l pulse width 3 t ihil3 m s peripheral input h pulse width 3 t ilih3 sense mode 8 t inst * m s peripheral input l pulse width 3 t ihil3 m s 0.2 v cc 0.8 v cc t ihil1 0.8 v cc int0 to 3 rti0, 1 0.2 v cc t ilih1 0.2 v cc 0.8 v cc t ihil2 0.8 v cc ec 0.2 v cc t ilih2 0.2 v cc 0.8 v cc t ihil3 0.8 v cc adst 0.2 v cc t ilih3
mb89660 series 34 (8) noise filter (v cc = +5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) parameter symbol pin condition value unit remarks min. max. noise filter width 1 t inf1 p30 to p37, p40 to p47, p60 to p63 during port operation 15 ns noise filter width 2 t inf2 p60 to p63 during external interrupt 60 ns t inf 1, 2 0.2 v cc t inf 1, 2 0.2 v cc input waveform 0.8 v cc 0.8 v cc
mb89660 series 35 5. a/d converter electrical characteristics (av cc = v cc = +3.5 v to 6.0 v, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst , see (4) instruction cycle in 4. ac characteristics. (1) a/d glossary ? resolution analog changes that are identifiable with the a/d converter. when the number of bits is 8, analog voltage can be divided into 2 8 = 256. ? linearity error (unit: lsb) the deviation of the straight line connecting the zero transition point (0000 0000 ? 0000 0001) with the full-scale transition point (1111 1111 ? 1111 1110) from actual conversion characteristics ? differential linearity error (unit: lsb) the deviation of input voltage needed to change the output code by 1 lsb from the theoretical value ? total error (unit: lsb) the difference between theoretical and actual conversion values parameter symbol pin condition value unit remarks min. typ. max. resolution 8bit total error avr = av cc 2.0 lsb linearity error 1.0 lsb differential linearity error 0.9 lsb zero transition voltage v ot av ss C 1.5 lsb av ss + 0.5 lsb av ss + 2.5 lsb mv full-scale transition voltage v fst avr C 3.5 lsb avr C 1.5 lsb avr + 0.5 lsb mv interchannel disparity 1lsb a/d mode conversion time 44 t isnt * m s sense mode conversion time 12 t inst * m s analog port input circuit i ain an0 to an7 10 m a analog input voltage 0avrv reference voltage avr 0av cc v reference voltage supply current i r avr = 5.0 v when a/d conversion is activated 150 m a i rh avr = 5.0 v when a/d conversion is stopped 5 m a
mb89660 series 36 (2) precautions ? input impedance of analog input pins the a/d converter used for the mb89660 series contains a sample hold circuit as illustrated below to fetch analog input voltage into the sample hold capacitor for eight instruction cycles after activating a/d conversion. for this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage might not stabilize within the analog input sampling period. therefore, it is recommended to keep the output impedance of the external circuit low. if a higher accurancy is required, set the output impedance in this series to 2 k w or less . when the impedance cannot be kept low, the following two methods are recommended. one is to activate the a/d converter continuously for obtaining the pseudo long sampling time by using software. the other is to connect the external capacitor of approx. 0.1 m s to the analog input pin. ?error the smaller the | avr C av ss |, the greater the error would become relatively. v ot v nt v ( n+i )t v fst digital output (1 lsb n + v ot ) 0000 0000 0000 0000 0001 0010 1111 1111 1110 1111 1 lsb = avr 256 linearity error = v nt - (1 lsb n + v ot ) 1 lsb differential linearity error = v ( n + 1 ) t - v nt 1 lsb analog input actual conversion value theoretical conversion value - 1 total error = 1 lsb v nt - (1 lsb n + 1 lsb) linearity error closes for 8 instruction cycles after activating a/d conversion. sample hold circuit c 33 pf analog channel selector analog input pin r 6 k w comparator if the output impedance of the external circuit is high, it is recommended to connect an external capacitor of approx. 0.1 m f. . . = . . = analog input equivalent circuit
mb89660 series 37 n examples characteristics 0 5 ?0 ?5 ?0 3.0 v dd - v oh2 (v) i oh2 (ma) v cc - v oh2 vs. i oh2 2.0 1.0 0 v cc = 3.0 v v cc = 4.0 v t a = +25? v cc = 5.0 v v cc = 6.0 v 010 123456789 0.1 0.2 0.3 0.4 0.5 v ol (v) v cc = 2.5 v v cc = 3.0 v v cc = 4.0 v v cc = 5.0 v v cc = 6.0 v i ol (ma) v ol vs. i ol t a = +25? 0.0 1.0 v dd - v oh (v) v cc = 2.5 v v cc = 3.0 v v cc = 4.0 v v cc = 5.0 v v cc = 6.0 v i oh (ma) v cc - v oh vs. i oh 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 ?.5 ?.0 ?.5 ?.0 ?.5 ?.0 t a = +25? 0 5 ?0 ?5 ?0 0.6 v ol2 (v) i ol2 (ma) v ol2 vs. i ol2 0.4 0.2 0 v cc = 3.0 v v cc = 4.0 v t a = +25? v cc = 5.0 v v cc = 6.0 v (1) l level output voltage p00 to p07, p10 to p17,p20 to p27, p30, p32 to p36, p40 to p47, p50 to p57, p60 to p63 (2) h level output voltage p00 to p07, p10 to p17, p20 to p27, p30, p32 to p36, p40 to p47, p60 to p63 (3) l level output voltage p31, p37 (4) h level output voltage p31, p37
mb89660 series 38 012 3 456 7 v cc (v) 5.0 v in (v) v in vs. v cc 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 t a = +25? v cc (v) i cc (ma) i cc vs. v cc 16 14 12 10 8 6 4 2 0 t a = +25? f c = 10 mhz f c = 8 mhz f c = 4 mhz f c = 1 mhz 123 456 7 v cc (v) i ccs (ma) i ccs vs. v cc 5 4 3 2 1 0 t a = +25? f c = 10 mhz f c = 8 mhz f c = 4 mhz f c = 1 mhz 123 456 7 (5) h level input voltage/l level input voltage (cmos input) (6) h level input voltage/l level input voltage (hysteresis input) (7) power supply current (external clock) 012 3 456 7 v cc (v) 5.0 v in (v) v in vs. v cc 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 v ihs v ils t a = +25? v ihs : v ils : threshold when input voltage in hysteresis characteristics is set to ??level threshold when input voltage in hysteresis characteristics is set to ??level
mb89660 series 39 r pulu vs. v cc 234 5 6 r pulu (k w ) 1 1 100 1000 t a = +25? v cc (v) (8) pull-up resistance
mb89660 series 40 n instructions (136 instructions) execution instructions can be divided into the following four groups: ? transfer ? arithmetic operation ? branch ?others table 1 lists symbols used for notation of instructions. table 1 instruction symbols columns indicate the following: mnemonic: assembler notation of an instruction ~: the number of instructions #: the number of bytes operation: operation of an instruction tl, th, ah: a content change when each of the tl, th, and ah instructions is executed. symbols in the column indicate the following: ? C indicates no change. ? dh is the 8 upper bits of operation description data. ? al and ah must become the contents of al and ah prior to the instruction executed. ? 00 becomes 00. n, z, v, c: an instruction of which the corresponding flag will change. if + is written in this column, the relevant instruction will change its corresponding flag. op code: code of an instruction. if an instruction is more than one code, it is written according to the following rule: example: 48 to 4f ? this indicates 48, 49, ... 4f. symbol meaning dir direct address (8 bits) off offset (8 bits) ext extended address (16 bits) #vct vector table number (3 bits) #d8 immediate data (8 bits) #d16 immediate data (16 bits) dir: b bit direct address (8:3 bits) rel branch relative address (8 bits) @ register indirect (example: @a, @ix, @ep) a accumulator a (whether its length is 8 or 16 bits is determined by the instruction in use.) ah upper 8 bits of accumulator a (8 bits) al lower 8 bits of accumulator a (8 bits) t temporary accumulator t (whether its length is 8 or 16 bits is determined by the instruction in use.) th upper 8 bits of temporary accumulator t (8 bits) tl lower 8 bits of temporary accumulator t (8 bits) ix index register ix (16 bits) ep extra pointer ep (16 bits) pc program counter pc (16 bits) sp stack pointer sp (16 bits) ps program status ps (16 bits) dr accumulator a or index register ix (16 bits) ccr condition code register ccr (8 bits) rp register bank pointer rp (5 bits) ri general-purpose register ri (8 bits, i = 0 to 7) indicates that the very is the immediate data. (whether its length is 8 or 16 bits is determined by the instruction in use.) ( ) indicates that the contents of is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.) (( )) the address indicated by the contents of is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.)
mb89660 series 41 table 2 transfer instructions (48 instructions) note during byte transfer to a, t ? a is restricted to low bytes. operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (reverse arrangement of f 2 mc-8 family) mnemonic ~ # operation tl th ah n z v c op code mov dir,a mov @ix +off,a mov ext,a mov @ep,a mov ri,a mov a,#d8 mov a,dir mov a,@ix +off mov a,ext mov a,@a mov a,@ep mov a,ri mov dir,#d8 mov @ix +off,#d8 mov @ep,#d8 mov ri,#d8 movw dir,a movw @ix +off,a movw ext,a movw @ep,a movw ep,a movw a,#d16 movw a,dir movw a,@ix +off movw a,ext movw a,@a movw a,@ep movw a,ep movw ep,#d16 movw ix,a movw a,ix movw sp,a movw a,sp mov @a,t movw @a,t movw ix,#d16 movw a,ps movw ps,a movw sp,#d16 swap setb dir: b clrb dir: b xch a,t xchw a,t xchw a,ep xchw a,ix xchw a,sp movw a,pc 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 5 4 2 3 4 5 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 3 1 1 3 2 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 (dir) ? (a) ( (ix) +off ) ? (a) (ext) ? (a) ( (ep) ) ? (a) (ri) ? (a) (a) ? d8 (a) ? (dir) (a) ? ( (ix) +off) (a) ? (ext) (a) ? ( (a) ) (a) ? ( (ep) ) (a) ? (ri) (dir) ? d8 ( (ix) +off ) ? d8 ( (ep) ) ? d8 (ri) ? d8 (dir) ? (ah),(dir + 1) ? (al) ( (ix) +off) ? (ah), ( (ix) +off + 1) ? (al) (ext) ? (ah), (ext + 1) ? (al) ( (ep) ) ? (ah),( (ep) + 1) ? (al) (ep) ? (a) (a) ? d16 (ah) ? (dir), (al) ? (dir + 1) (ah) ? ( (ix) +off), (al) ? ( (ix) +off + 1) (ah) ? (ext), (al) ? (ext + 1) (ah) ? ( (a) ), (al) ? ( (a) ) + 1) (ah) ? ( (ep) ), (al) ? ( (ep) + 1) (a) ? (ep) (ep) ? d16 (ix) ? (a) (a) ? (ix) (sp) ? (a) (a) ? (sp) ( (a) ) ? (t) ( (a) ) ? (th),( (a) + 1) ? (tl) (ix) ? d16 (a) ? (ps) (ps) ? (a) (sp) ? d16 (ah) ? (al) (dir): b ? 1 (dir): b ? 0 (al) ? (tl) (a) ? (t) (a) ? (ep) (a) ? (ix) (a) ? (sp) (a) ? (pc) C C C C C al al al al al al al C C C C C C C C C al al al al al al C C C C C C C C C C C C C C C al al C C C C C C C C C C C C C C C C C C C C C C C C C ah ah ah ah ah ah C C C C C C C C C C C C C C C C ah C C C C C C C C C C C C C C C C C C C C C C C C C dh dh dh dh dh dh dh C C dh C dh C C C dh C C al C C C dh dh dh dh dh C C C C C C C C C C C C C C C C C C C C + + C C + + C C + + C C + + C C + + C C + + C C + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + C C + + C C + + C C + + C C + + C C + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 45 46 61 47 48 to 4f 04 05 06 60 92 07 08 to 0f 85 86 87 88 to 8f d5 d6 d4 d7 e3 e4 c5 c6 c4 93 c7 f3 e7 e2 f2 e1 f1 82 83 e6 70 71 e5 10 a8 to af a0 to a7 42 43 f7 f6 f5 f0
mb89660 series 42 table 3 arithmetic operation instructions (62 instructions) (continued) mnemonic ~ # operation tl th ah n z v c op code addc a,ri addc a,#d8 addc a,dir addc a,@ix +off addc a,@ep addcw a addc a subc a,ri subc a,#d8 subc a,dir subc a,@ix +off subc a,@ep subcw a subc a inc ri incw ep incw ix incw a dec ri decw ep decw ix decw a mulu a divu a andw a orw a xorw a cmp a cmpw a rorc a rolc a cmp a,#d8 cmp a,dir cmp a,@ep cmp a,@ix +off cmp a,ri daa das xor a xor a,#d8 xor a,dir xor a,@ep xor a,@ix +off xor a,ri and a and a,#d8 and a,dir 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 2 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 (a) ? (a) + (ri) + c (a) ? (a) + d8 + c (a) ? (a) + (dir) + c (a) ? (a) + ( (ix) +off) + c (a) ? (a) + ( (ep) ) + c (a) ? (a) + (t) + c (al) ? (al) + (tl) + c (a) ? (a) - (ri) - c (a) ? (a) - d8 - c (a) ? (a) - (dir) - c (a) ? (a) - ( (ix) +off) - c (a) ? (a) - ( (ep) ) - c (a) ? (t) - (a) - c (al) ? (tl) - (al) - c (ri) ? (ri) + 1 (ep) ? (ep) + 1 (ix) ? (ix) + 1 (a) ? (a) + 1 (ri) ? (ri) - 1 (ep) ? (ep) - 1 (ix) ? (ix) - 1 (a) ? (a) - 1 (a) ? (al) (tl) (a) ? (t) / (al),mod ? (t) (a) ? (a) (t) (a) ? (a) (t) (a) ? (a) " (t) (tl) - (al) (t) - (a) (a) - d8 (a) - (dir) (a) - ( (ep) ) (a) - ( (ix) +off) (a) - (ri) decimal adjust for addition decimal adjust for subtraction (a) ? (al) " (tl) (a) ? (al) " d8 (a) ? (al) " (dir) (a) ? (al) " ( (ep) ) (a) ? (al) " ( (ix) +off) (a) ? (al) " (ri) (a) ? (al) (tl) (a) ? (al) d8 (a) ? (al) (dir) C C C C C C C C C C C C C C C C C C C C C C C dl C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 00 C C C C C C C C C C C C C C C C C C C C C C C C C C C C dh C C C C C C dh C C C C dh C C C dh dh 00 dh dh dh C C C C C C C C C C C C C C C C C C C C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + C C C C C C C C C + + C C + + + C C C C C C C C C + + C C C C C C C C C C + + r C + + r C + + r C + + + + + + + + + + C + + + C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C 28 to 2f 24 25 26 27 23 22 38 to 3f 34 35 36 37 33 32 c8 to cf c3 c2 c0 d8 to df d3 d2 d0 01 11 63 73 53 12 13 03 02 14 15 17 16 18 to 1f 84 94 52 54 55 57 56 58 to 5f 62 64 65 a c ? ? ?? a c
mb89660 series 43 (continued) table 4 branch instructions (17 instructions) table 5 other instructions (9 instructions) mnemonic ~ # operation tl th ah n z v c op code and a,@ep and a,@ix +off and a,ri or a or a,#d8 or a,dir or a,@ep or a,@ix +off or a,ri cmp dir,#d8 cmp @ep,#d8 cmp @ix +off,#d8 cmp ri,#d8 incw sp decw sp 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 (a) ? (al) ( (ep) ) (a) ? (al) ( (ix) +off) (a) ? (al) (ri) (a) ? (al) (tl) (a) ? (al) d8 (a) ? (al) (dir) (a) ? (al) ( (ep) ) (a) ? (al) ( (ix) +off) (a) ? (al) (ri) (dir) C d8 ( (ep) ) C d8 ( (ix) + off) C d8 (ri) C d8 (sp) ? (sp) + 1 (sp) ? (sp) C 1 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + + + + + + + + + + + + + + + C C C C C C C C 67 66 68 to 6f 72 74 75 77 76 78 to 7f 95 97 96 98 to 9f c1 d1 mnemonic ~ # operation tl th ah n z v c op code bz/beq rel bnz/bne rel bc/blo rel bnc/bhs rel bn rel bp rel blt rel bge rel bbc dir: b,rel bbs dir: b,rel jmp @a jmp ext callv #vct call ext xchw a,pc ret reti 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 if z = 1 then pc ? pc + rel if z = 0 then pc ? pc + rel if c = 1 then pc ? pc + rel if c = 0 then pc ? pc + rel if n = 1 then pc ? pc + rel if n = 0 then pc ? pc + rel if v " n = 1 then pc ? pc + rel if v " n = 0 then pc ? pc + rei if (dir: b) = 0 then pc ? pc + rel if (dir: b) = 1 then pc ? pc + rel (pc) ? (a) (pc) ? ext vector call subroutine call (pc) ? (a),(a) ? (pc) + 1 return from subrountine return form interrupt C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C dh C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + C C C + C C C C C C C C C C C C C C C C C C C C C C C C C C restore fd fc f9 f8 fb fa ff fe b0 to b7 b8 to bf e0 21 e8 to ef 31 f4 20 30 mnemonic ~ # operation tl th ah n z v c op code pushw a popw a pushw ix popw ix nop clrc setc clri seti 4 4 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C C C C C C C C C C C C C C C C C C C dh C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C r C C C s C C C C C C C C 40 50 41 51 00 81 91 80 90
mb89660 series 44 n instruction map h l 0123456789abcdef 0 nop swap ret reti pushw a popw a mov a,ext movw a,ps clri seti clrb dir: 0 bbc dir: 0,rel incw a decw a jmp @a movw a,pc 1 mulu a divu a jmp addr16 call addr16 pushw ix popw ix mov ext,a movw ps,a clrc setc clrb dir: 1 bbc dir: 1,rel incw sp decw sp movw sp,a movw a,sp 2 rolc a cmp a addc a subc a xch a, t xor a and a or a mov @a,t mov a,@a clrb dir: 2 bbc dir: 2,rel incw ix decw ix movw ix,a movw a,ix 3 rorc a cmpw a addcw a subcw a xchw a, t xorw a andw a orw a movw @a,t movw a,@a clrb dir: 3 bbc dir: 3,rel incw ep decw ep movw ep,a movw a,ep 4 mov a,#d8 cmp a,#d8 addc a,#d8 subc a,#d8 xor a,#d8 and a,#d8 or a,#d8 daa das clrb dir: 4 bbc dir: 4,rel movw a,ext movw ext,a movw a,#d16 xchw a,pc 5 mov a,dir cmp a,dir addc a,dir subc a,dir mov dir,a xor a,dir and a,dir or a,dir mov dir,#d8 cmp dir,#d8 clrb dir: 5 bbc dir: 5,rel movw a,dir movw dir,a movw sp,#d16 xchw a,sp 6 mov a,@ix +d cmp a,@ix +d addc a,@ix +d subc a,@ix +d mov @ix +d,a xor a,@ix +d and a,@ix +d or a,@ix +d mov @ix +d,#d8 cmp @ix +d,#d8 clrb dir: 6 bbc dir: 6,rel movw a,@ix +d movw @ix +d,a movw ix,#d16 xchw a,ix 7 mov a,@ep cmp a,@ep addc a,@ep subc a,@ep mov @ep,a xor a,@ep and a,@ep or a,@ep mov @ep,#d8 cmp @ep,#d8 clrb dir: 7 bbc dir: 7,rel movw a,@ep movw @ep,a movw ep,#d16 xchw a,ep 8 mov a,r0 cmp a,r0 addc a,r0 subc a,r0 mov r0,a xor a,r0 and a,r0 or a,r0 mov r0,#d8 cmp r0,#d8 setb dir: 0 bbs dir: 0,rel inc r0 dec r0 callv #0 bnc rel 9 mov a,r1 cmp a,r1 addc a,r1 subc a,r1 mov r1,a xor a,r1 and a,r1 or a,r1 mov r1,#d8 cmp r1,#d8 setb dir: 1 bbs dir: 1,rel inc r1 dec r1 callv #1 bc rel a mov a,r2 cmp a,r2 addc a,r2 subc a,r2 mov r2,a xor a,r2 and a,r2 or a,r2 mov r2,#d8 cmp r2,#d8 setb dir: 2 bbs dir: 2,rel inc r2 dec r2 callv #2 bp rel b mov a,r3 cmp a,r3 addc a,r3 subc a,r3 mov r3,a xor a,r3 and a,r3 or a,r3 mov r3,#d8 cmp r3,#d8 setb dir: 3 bbs dir: 3,rel inc r3 dec r3 callv #3 bn rel c mov a,r4 cmp a,r4 addc a,r4 subc a,r4 mov r4,a xor a,r4 and a,r4 or a,r4 mov r4,#d8 cmp r4,#d8 setb dir: 4 bbs dir: 4,rel inc r4 dec r4 callv #4 bnz rel d mov a,r5 cmp a,r5 addc a,r5 subc a,r5 mov r5,a xor a,r5 and a,r5 or a,r5 mov r5,#d8 cmp r5,#d8 setb dir: 5 bbs dir: 5,rel inc r5 dec r5 callv #5 bz rel e mov a,r6 cmp a,r6 addc a,r6 subc a,r6 mov r6,a xor a,r6 and a,r6 or a,r6 mov r6,#d8 cmp r6,#d8 setb dir: 6 bbs dir: 6,rel inc r6 dec r6 callv #6 bge rel f mov a,r7 cmp a,r7 addc a,r7 subc a,r7 mov r7,a xor a,r7 and a,r7 or a,r7 mov r7,#d8 cmp r7,#d8 setb dir: 7 bbs dir: 7,rel inc r7 dec r7 callv #7 blt rel
mb89660 series 45 n mask options n ordering information no. part number mb89663 mb89665 mb89p665 mb89w665 specifying procedure specify when ordering masking set with eprom programmer 1 power-on reset selection with power-on reset without power-on reset selectable setting possible 2 selection of the oscillation stabilization time crystal oscillator (26.2 ms/10 mhz) ceramic oscillator (1.64 ms/10 mhz) selectable setting possible 3 reset pin output with reset output without reset output selectable setting possible 4 pull-up resistors p00 to p07, p10 to p17, p30 to p37, p40 to p47, p50 to p57, p60 to p63 can be selected per pin. (p50 to p57 are available for without pull-up resistors when an a/d converter is used.) can be set per pin. (p54 to p57 must have the same setting) part number package remarks MB89663P-SH mb89665p-sh mb89p665p-sh 64-pin plastic sh-dip (dip-64p-m01) mb89663pf mb89665pf mb89p665pf 64-pin plastic sh-dip (fpt-64p-m06) mb89w665c-sh 64-pin ceramic sh-dip (dip-64c-a06)
mb89660 series 46 n package dimensions "a" lead no. 64 52 32 0.25(.010) 0.30(.012) 51 33 1 19 20 index typ (.016.004) 0.400.10 1.00(.0394) 0.150.05(.006.002) 18.00(.709)ref 22.300.40(.878.016) (stand off) 0.05(.002)min 3.35(.132)max (.551.008) 14.000.20 (.642.016) 16.300.40 ref 12.00(.472) (.736.016) 18.700.40 20.000.20(.787.008) 24.700.40(.972.016) (.047.008) details of "b" part 1.200.20 0 10 details of "a" part 0.18(.007)max 0.63(.025)max 0.10(.004) "b" m 0.20(.008) 1994 fujitsu limited f64013s-3c-2 c +0.50 C0 C0 +.020 C.022 +.008 C0.55 +0.22 55.118(2.170)ref index-2 15max typ 19.05(.750) (.010.002) 0.250.05 max 1.778(.070) (.070.007) 1.7780.18 1.00 .039 (.018.004) 0.450.10 0.51(.020)min 3.00(.118)min 5.65(.222)max index-1 (.669.010) 17.000.25 2.283 58.00 1994 fujitsu limited d64001s-3c-4 c 64-pin plastic sh-dip (dip-64p-m01) dimensions in mm (inches) 64-pin plastic qfp (fpt-64p-m06) dimensions in mm (inches)
mb89660 series 47 +0.13 C0.08 C.003 +.005 0~9 5.84(.230)max 8.89(.350) dia typ (.134.014) 3.400.36 55.118(2.170)ref (.738.010) 18.750.25 (2.240.022) 56.900.56 (.750.010) 19.050.25 (.010.004) 0.250.05 1.270.25 (.050.010) 1.45(.057) max 1.7780.180 (.070.007) 0.900.10 (.0355.0040) 0.46 .018 index area r1.27(.050) ref 1994 fujitsu limited d64006sc-1-2 c dimensions in mm (inches) 64-pin ceramic sh-dip (dip-64c-a06)
mb89660 series fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka, nakahara-ku, kawasaki-shi, kanagawa 211-8588, japan tel: +81-44-754-3763 fax: +81-44-754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. 3545 north first street, san jose, ca 95134-1804, u.s.a. tel: +1-408-922-9000 fax: +1-408-922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: +1-800-866-8608 fax: +1-408-922-9179 http://www.fujitsumicro.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www.fujitsu-fme.com/ asia pacific fujitsu microelectronics asia pte. ltd. #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-281-0770 fax: +65-281-0220 http://www.fmap.com.sg/ korea fujitsu microelectronics korea ltd. 1702 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 f9602 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the contents of this document may not be reproduced or copied without the permission of fujitsu limited. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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